1. Field of Invention
The present invention relates to a display apparatus. More particularly, the present invention relates to a liquid crystal display panel capable of improving display quality.
2. Description of Related Art
Due to the progress of semiconductor devices or display apparatuses, current multimedia technology is well developed. Among displays, thin film transistor liquid crystal displays (TFT LCD) characterized in high picture quality, good space utilization, low power consumption, and no radiation etc. have gradually become mainstream products in the market.
An common TFT LCD is mainly constituted of a TFT array substrate, a color filter substrate, and a liquid crystal layer sandwiched between the above two substrates. The TFT array substrate has a plurality of pixel electrodes disposed thereon, the color filter substrate has a common electrode layer disposed thereon, and the liquid crystal layer is controlled by the electric field between the pixel electrodes and the common electrode layer. The TFT array substrate is mainly formed by a mask process. For example, in the conventional five mask processes, the first mask process mainly defines the gate and scan line; the second mask process mainly defines the channel layer; the third mask process mainly defines the source, drain, and data line; the fourth mask process mainly defines the passivation layer; and the fifth mask process mainly defines the pixel electrode.
However, currently, the exposure method adopted in a mask process is mainly achieved by the use of a stepper or scanner. Referring to FIG. 1, as for a stepper, when the dimension of the mask is smaller than a substrate 110, the substrate 110 must be divided into a plurality of shots 10 for performing several exposures to complete exposing the entire region required on the substrate 110. For example, a 12-inch or 14-inch substrate must be exposed four times, and a 15-inch or 17-inch substrate 110 must be exposed six times. It should be noted that the more the shot 10 is, the easier the alignment offset between the shots 10 occurs. Therefore, the film layers formed at different positions in the shots 10 may have offset to some extent.
FIG. 2 is a partial schematic view of the pixel structure on a conventional TFT array substrate. Referring to FIG. 2, a conventional pixel structure 100 mainly comprises a TFT 122, a pixel electrode 124, a scan line 126, and a data line 128. The pixel electrode 124 is electrically connected to the corresponding scan line 126 and data line 128 through the TFT 122. It should be noted that a region 20 overlapped by a gate 122g and a drain 122d together with a region 30 overlapped by the pixel electrode 124 and the scan line 126 generates a gate-drain parasitic capacitance Cgd effect, and the value of the gate-drain parasitic capacitance Cgd is in direct proportion to the area of the regions 20, 30.
Generally, when fabricating the TFT, due to factors such as errors in the alignment of the mask or vibration, the area of the regions 20, 30 respectively overlapped by the gate 122g and drain 122d changes. As a result, the value of the gate-drain parasitic capacitance Cgd varies in the shots 10 at different positions. However, the value of the gate-drain parasitic capacitance Cgd may directly affect the pixel feedback voltage used for driving the liquid crystal molecules. If the difference between the pixel feedback voltages in shots 10 at different positions is too great, a problem of shot mura may occur to the display frame of the TFT LCD at the edges of the shots.